
library ieee;
use ieee.std_logic_1164.all;

entity nios_top_level is
	port (
	-- CLOCK
	CLOCK_50	: in std_logic;
	LED		: out std_logic_vector(7 downto 0);
	KEY		: in std_logic_vector(1 downto 0);
	SW		: in std_logic_vector(3 downto 0);

	-- SDRAM
	DRAM_ADDR	: out std_logic_vector(12 downto 0);
	DRAM_BA		: out std_logic_vector(1 downto 0);
	DRAM_CAS_N	: out std_logic;
	DRAM_CKE	: out std_logic;
	DRAM_CLK	: out std_logic;
	DRAM_CS_N	: out std_logic;
	DRAM_DQ		: inout std_logic_vector(15 downto 0);
	DRAM_DQM	: out std_logic_vector(1 downto 0);
	DRAM_RAS_N	: out std_logic;
	DRAM_WE_N	: out std_logic;

	-- GPIO_0, GPIO_0 connect to GPIO Default
	GPIO_0		: inout std_logic_vector(33 downto 0);
	GPIO_0_IN	: in    std_logic_vector(1 downto 0);

	-- GPIO_1, GPIO_1 connect to GPIO Default
	GPIO_1		: inout std_logic_vector(33 downto 0);
	GPIO_1_IN	: in    std_logic_vector(1 downto 0)
	);
end entity;


architecture behavior of nios_top_level is
	signal locked_from_the_pll : std_logic;
	signal count_horz, count_vert : std_logic_vector(10 downto 0);
	signal direction_horz, direction_vert, pwm_horz, pwm_vert : std_logic;
	signal txd_from_the_uart_0, rxd_to_the_uart_0 : std_logic;
begin

  DE0_Nano_system_inst : work.DE0_Nano_system
    port map(
		direction_from_the_pwm_0 => direction_horz,
      pwm_out_from_the_pwm_0 => pwm_horz,
		direction_from_the_pwm_1 => direction_vert,
		pwm_out_from_the_pwm_1 => pwm_vert,
		user_output_from_the_quadrature_0 => count_horz,
		user_output_from_the_quadrature_1 => count_vert,
      channelA_to_the_quadrature_0 => GPIO_0(22), -- horizontal
      channelB_to_the_quadrature_0 => GPIO_0(23), -- horizontal
      channelA_to_the_quadrature_1 => GPIO_0(24), --vertical
      channelB_to_the_quadrature_1 => GPIO_0(25), --vertical
      sdram_clk => DRAM_CLK,
      zs_addr_from_the_sdram => DRAM_ADDR,
      zs_ba_from_the_sdram => DRAM_BA,
      zs_cas_n_from_the_sdram => DRAM_CAS_N,
      zs_cke_from_the_sdram => DRAM_CKE,
      zs_cs_n_from_the_sdram => DRAM_CS_N,
      zs_dq_to_and_from_the_sdram => DRAM_DQ,
      zs_dqm_from_the_sdram => DRAM_DQM,
      zs_ras_n_from_the_sdram => DRAM_RAS_N,
      zs_we_n_from_the_sdram => DRAM_WE_N,
      areset_to_the_pll => '0',
      ext_clk => CLOCK_50,
      reset_n => '1',
		txd_from_the_uart_0 => txd_from_the_uart_0,
      rxd_to_the_uart_0 => rxd_to_the_uart_0
    );
	 
	 GPIO_0(6) <= txd_from_the_uart_0;
	 rxd_to_the_uart_0 <= GPIO_0(7);
	 
	 GPIO_1(11) <= direction_horz;
	 GPIO_1(9) <= pwm_horz;
	 
	 GPIO_1(10) <= direction_vert;
	 GPIO_1(8) <= pwm_vert;
	 
    LED <= (0=>pwm_horz, 1=>direction_horz, 2=>pwm_vert, 3=>direction_vert, 4=>'1', others=>'0');
end architecture;
